Personal computers can be connected to various peripheral components using peripheral component interconnect (PCI) connectors. Since its inception in 1992, the PCI bus has become the input/output standard of most computing platforms. Computer central processing units can be connected, using PCI architecture, to hard disk drives, printers, networks, and various other components. This relatively old connector/interface technology, however, has resulted in bottlenecks as newer, higher speed, more powerful computer components have been introduced.
Not surprisingly, the PCI technology has evolved by offloading various functions to higher-bandwidth PCI derivatives, including AGP and PCI-X, both of which are PCI variants. Unfortunately, the PCI bus cannot be easily scaled up in frequency or down in voltage. In addition, the PCI bus does not support features such as advanced power management, native hot plugging/hot swapping of peripherals, or quality of service to guarantee bandwidth for real-time operations. Finally, all of the available bandwidth of the PCI bus is limited to one direction of communication (send or receive) at a time. This is a drawback because many communication networks support simultaneous bidirectional traffic, which minimizes message latency.
A relatively new connector architecture known as PCI express (formerly “3GIO”) has been introduced which uses four wires of two differential pairs to support simultaneous two-way communication. More particularly, PCI express uses a high speed serial link (unlike 32 bit and 64 bit parallel buses) that consists of dual simplex channels, each implemented as a transmit pair and a receive pair for simultaneous transmission in each direction. Each pair consists of two low-voltage, differentially driven pairs of signals. A PCI Express link can be scaled by adding signal pairs to form multiple lanes between two devices, with one bit (×1), four bit (×4), eight bit (×8), and sixteen bit (×16) lane widths being supported.
With that overview of PCI express in mind, the present invention recognizes that the PCI express architecture can support components having connectors (i.e., ×1, ×4, ×8, and ×16) of various sizes, ranging from smallest (×1), requiring the fewest connector elements, to the largest (×16) such as some video cards, which requires all 164 connector elements of a PCI express connector. In other words, a single PCI express connector on the motherboard of a computer is expected to support component connectors of various sizes. However, as understood herein some computers and/or their operating systems might not be configured to operate with components having larger (e.g., ×16) connectors. Nevertheless, the presence of the single PCI express connector might induce a user to unwittingly plug into the connector an unsupported component, on the erroneous assumption that the component is supported by the computer. This invention is directed to that problem.